1st Asia NetFPGA Developers Workshop Program

 June 14, 2010 at KAIST, Daejeon, Korea

 

 June 13, 2010

11:00 ~

Preparation and Test for the demonstration of papers

At workshop venue : Room #4443 (Oh SangSu Seminar Room, 4th floor of KAIST CS Building(E3-1)

June 14, 2010

09:00 ~ 10:00

Registration

10:00 ~ 12:00

Tutorial Session : Dr. John Lockwood (ALGO-LOGIC, CEO)

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"Building Networks with Open, Reconfigurable Hardware"

 

The NetFPGA is an open hardware platform that provides Gigabit/second, line rate processing using Field Programmable Gate Arrays.    The platform has been used to implement several reference circuits that include a network interface card, an Ethernet switch, and Internet router, an OpenFlow switch, and a traffic generator.   The NetFPGA integrates into an x86 PC and a Linux device driver is provided that allows the host to send and receive packets between the CPU and the FPGA.   This talk will overview the methodology of building applications that run on the NetFPGA, discuss the structure of the source code tree, and review some of the new projects that have been contributed to the open-source community.   Algo included will be a brief discussion of the FPX, another FPGA-based networking platform that was used to implement a complete system-on-chip (SoC) Internet Firewall with IDS and IDP features.   Examples of how Regular Expression (RegEx) matching can be accelerated through use of a large number of parallel state machines and how a TCAM can be implemented in FPGA hardware will be provided.  Finally, the talk will conclude with a preview of the upcoming NetFPGA 10G card and introduce Algo-Logic (TM) Systems--a new company that designs Algorithms that run in Logic and supports multiple open hardware platforms.

12:00 ~ 13:00

Lunch

13:00 ~ 15:40

Technical Session 1 (Chair: Seung Yeob Nam, Yeungnam Univ)

1-1

Implementation of a Programmable Service Composition Network using NetFPGA-based OpenFlow Switches

Seok Hong Min(CNU, KR), Yoon Cheol Choi(CNU, KR), Namgon Kim(GIST, KR), Wan Kim(POSTECH, KR), Oh Chan Kwon(POSTECH, KR), Byung Chul Kim(CNU, KR), Jae Yong Lee(CNU, KR), Dae Yong Kim(CNU, KR), Jongwon Kim(GIST, KR), Hwangjun Song (POSTECH, KR)

1-2

Implementing On-line Sketch-Based Change Detection on a NetFPGA Platform

Yu-Kuen Lai, Nan-Cheng Wang, Tze-Yu Chou, Chun-Chieh Lee, Theophilus Wellem, Hargyo Tri Nugroho(Chung-Yuan Christian Univ., TW)

1-3

Implementation of the hardwired AFDX NIC

Pusik Park(KETI, KR), Hangyun Jung(KETI, KR), Daekyo Shin(KETI, KR), Kitaeg Lim(KETI, KR), Jongho Yoon(Korea Aerospace Univ. KR)

1-4

Data Center Quantized Congestion Notification (QCN): Implementation and Evaluation on NetFPGA

Abdul Kabbani(Stanford Univ., US), Masato Yasuda(NEC, JP)

15:40 ~ 16:00

Break

16:00 ~ 18:40

Technical Session 2 (Chair: Hwangjun Song, POSTECH)

2-1

Mitigating HTTP GET Flooding Attacks through Modified NetFPGA Reference Router

Jinghe Jin(Yungnam Univ, KR), Nazarov Nodir((Yungnam Univ, KR), Chaetae Im(KISA, KR),

 Seung Yeob Nam (Yungnam Univ, KR)

2-2

Pattern Based Packet Filtering using NetFPGA in DETER infrastructure

Andrew Goodney, Shailesh Narayan, Vivek Bhandwalkar, Young H. Cho(USC, US)

2-3

A Network Emulator on the NetFPGA Platform

Seok Hong Min, Jae Young Lee, Byung Chul Kim(CNU, KR)

2-4

Remodeling the NetFPGA architecture for content processing and filtering

Bokil Kanchan (C-DAC, IN)

18:40 ~ 18:50

Closing